Arm Architecture

Topics: ARM architecture, Central processing unit, Memory management unit Pages: 42 (5293 words) Published: June 28, 2013
ARM Processor Architecture

Some Slides are Adopted from NCTU IP Core Design Some Slides are Adopted from NTU Digital SIP Design Project SOC Consortium Course Material

ARM Core Family ARM Processor Core Introduction to Several ARM processors Memory Hierarchy Software Development Summary

SOC Consortium Course Material


ARM Core Family

SOC Consortium Course Material


ARM Core Family
Application Cores ARM Cortex-A8 ARM Cortex-A9 MPCore ARM Cortex-A9 Single Core ARM11 MPCore ARM1136J(F)-S ARM1176JZ(F)-S ARM720T ARM920T ARM922T ARM926EJ-S Embedded Cores ARM Cortex-M10 ARM Cortex-M1 ARM Cortex-M3 ARM Cortex-R4(F) ARM1156T2(F)-S ARM7EJ-S ARM7TDMI ARM7TDMI-S ARM946E-S ARM966E-S ARM968E-S ARM996HS SOC Consortium Course Material 4

Secure Cores SecurCore SC100 SecurCore SC110 SecurCore SC200 SecurCore SC210

Product Code Demystified

T: Thumb D: On-chip debug support M: Enhanced multiplier I: Embedded ICE hardware T2: Thumb-2 S: Synthesizable code E: Enhanced DSP instruction set J: JAVA support, Jazelle Z: Should be TrustZone? F: Floating point unit H: Handshake, clockless design for synchronous or asynchronous design SOC Consortium Course Material 5

ARM Processor Cores (1/4)

ARM processor core + cache + MMU → ARM CPU cores ARM6 → ARM7 – – – – 3-stage pipeline Keep its instructions and data in the same memory system Thumb 16-bit compressed instruction set On-chip Debug support, enabling the processor to halt in response to a debug request – Enhanced Multiplier, 64-bit result – Embedded ICE hardware, give on-chip breakpoint and watchpoint support

SOC Consortium Course Material


ARM Processor Cores (2/4)

ARM8 → ARM9 → ARM10 ARM9
– 5-stage pipeline (130 MHz or 200MHz) – Using separate instruction and data memory ports

ARM 10 (1998. Oct.)
– High performance, 300 MHz – Multimedia digital consumer applications – Optional vector floating-point unit SOC Consortium Course Material 7

ARM Processor Cores (3/4)
ARM11 (2002 Q4)
• 8-stage pipeline • Addresses a broad range of applications in the wireless, consumer, networking and automotive segments • Support media accelerating extension instructions • Can achieve 1GHz • Support AXI

SecurCore Family
– Smart card and secure IC development

SOC Consortium Course Material


ARM Processor Cores (4/4)
Cortex Family
– Provides a large range of solutions optimized around specific market applications across the full performance spectrum – ARM Cortex-A Series, applications processors for complex OS and user applications. • Supports the ARM, Thumb and Thumb-2 instruction sets

– ARM Cortex-R Series, embedded processors for real-time systems. • Supports the ARM, Thumb, and Thumb-2 instruction sets

– ARM Cortex-M Series, deeply embedded processors optimized for cost sensitive applications. • Supports the Thumb-2 instruction set only

SOC Consortium Course Material


ARM Processor Core

SOC Consortium Course Material


ARM Architecture Version (1/6)
Version 1
– The first ARM processor, developed at Acorn Computers Limited 1983-1985 – 26-bit address, no multiply or coprocessor support

Version 2
– Sold in volume in the Acorn Archimedes and A3000 products – 26-bit addressing, including 32-bit result multiply and coprocessor

Version 2a
– Coprocessor 15 as the system control coprocessor to manage cache – Add the atomic load store (SWP) instruction

SOC Consortium Course Material


ARM Architecture Version (2/6)
Version 3
– First ARM processor designed by ARM Limited (1990) – ARM6 (macro cell) ARM60 (stand-alone processor) ARM600 (an integrated CPU with on-chip cache, MMU, write buffer) ARM610 (used in Apple Newton) – 32-bit addressing, separate CPSR and SPSRs – Add the undefined and abort modes to allow coprocessor emulation and virtual memory support in supervisor mode

Version 3M
– Introduce the signed and unsigned multiply and multiplyaccumulate instructions that generate...
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