expanding opcodes

Topics: Computer architecture, Central processing unit, Instruction set Pages: 8 (1262 words) Published: December 12, 2014
Exam 2 Review Session Spring 2012
Topics
Chap. 4

The Microarchitecture Level

IJVM Mic-1, instructions set architecture and control flow.
Speeding up the Mic-1 architecture (Mic-1 to Mic-4):
Multiple internal busses, instruction fetch unit (IFU), instruction prefetching, pipelining, etc. Other Means to Improve Performance:
Cache, Branch Predication (Static and Dynamic), Out-of-order Execution, Register Renaming, Speculative Execution, etc.
Application of improvements in Pentium class architectures

Chap. 5

The Instruction Set Architecture Level

Programmer’s and User’s Manual for a Processor
Architecture, Data Types, Addressing and Memory Maps
Instruction Formats:
0, 1, 2, 3, 4 – Address Instructions
Opcode composition, Opcode Design (Expanding Opcodes)
Addressing Modes:
Immediate, direct, register, register indirect, indexed, based-indexed, stack, PC-Relative Instruction Types:
Data Movement, Dyadic, Monadic, Comparisons and Conditional Branches, Procedure Calls, Loop Control, Input and Output
Flow Control:
Procedures, Coroutines, Traps, and Interrupts
Improving Performance:
Predication, Speculative Execution, Speculative Load etc.

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Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.

Exam Expected Format:
7-8 Questions Likely
2005
2004fa
2004sp
2003
2002
2001

7
7
7
7
8
7

Short answer question with multiple parts 2/4 points each, total 10/20 points. Simple 5 point questions, or multiple part 5 point each question. Basic 10 point questions, multiple parts can be expected.

Back of the envelope computation question(s).

All Chap. 4-5 topics … and anything recovered or extended. IJVM MIC-1 architecture
IJVM new instruction sequence
IJVM Stack based code execution
IJVM instruction execution register content timing
ISAs for different microarchitectures
Addressing modes and Opcode Construction
Flow Control
Advanced Processor Features and Speed Improvements
Cache

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Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.

5.26) How can you clear a memory word on a machine with no CLR instructions? It obviously depends on the machine, but typically you would generate a zero in a register and then store the value to memory. You can generate a zero in a register by loading the constant zero from memory, by subtracting a number from itself, or by EXCLUSIVE ORing a number with itself.

5.18) In Fig. 5-24, bit 23 is used to distinguish the use of format 1 from format 2. No bit is provided to distinguish the use of format 3, however. How does the hardware know to use it? The use of format 3 is inherent in the opcode. An instruction like ADD uses either format 1 or format 2, depending upon bit 23, but an instruction like BEQ always uses format 3. It does not have to be told to do so.

Note: Ways to identify instruction formats:
1)

Explicit bits in the formatting field (UltraSPARC 2-bits define 4 basic formats)

2)

Expanding Op-Codes, where specific bit patterns describe the instruction fields

3)

A combination of the two methods … basic formats with some also extended

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Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.

5.3) Design an expanding opcode to allow all the following to be encoded in a 36-bit instruction: 7 instructions with two 15-bit addresses and one 3-bit register number 500 instructions with one 15-bit address and one 3-bit register number 50 instructions with no addresses or registers.

The first format consists of a 3-bit opcode, two 15-bit address fields and one 3-bit...
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